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data sheet, v1.0, jan. 2005 microcontrollers never stop thinking. xc164s 16-bit single-chip microcontroller with c166sv2 core
edition 2005-01 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
data sheet, v1.0, jan. 2005 microcontrollers never stop thinking. xc164s 16-bit single-chip microcontroller with c166sv2 core
template: mc_a5_ds_tmplt.fm / 4 / 2004-09-15 controller area network (can): license of robert bosch gmbh xc164s revision history: 2005-01 v1.0 previous version: none page subjects (major changes since last revision) we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
xc164s derivatives data sheet 1 v1.0, 2005-01 table of contents 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 general device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 pin configuration and definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 memory subsystem and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 external bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 central processing unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 on-chip debug support (ocds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.6 capture/compare units (capcom1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.7 the capture/compare unit capcom6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.8 general purpose timer (gpt12e) unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.9 real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.10 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.11 asynchronous/synchronous serial interfaces (asc0/asc1) . . . . . . . . . . 37 3.12 high speed synchronous serial channels (ssc0/ssc1) . . . . . . . . . . . . 38 3.13 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.14 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.15 parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.16 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.17 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2 package properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.4 parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.5 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.6 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5 timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.1 definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 external clock drive xtal1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.3 testing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
xc164s derivatives summary of features data sheet 2 v1.0, 2005-01 1 summary of features ? high performance 16-bit cpu with 5-stage pipeline ? 25 ns instruction cycle time at 40 mhz cpu clock (single-cycle execution) ? 1-cycle multiplication (16 16 bit), background division (32 / 16 bit) in 21 cycles ? 1-cycle multiply-and-accumulate (mac) instructions ? enhanced boolean bit manipulation facilities ? zero-cycle jump execution ? additional instructions to support hll and operating systems ? register-based design with multiple variable register banks ? fast context switching support with two additional local register banks ? 16 mbytes total linear address space for code and data ? 1024 bytes on-chip special function register area (c166 family compatible) ? 16-priority-level interrupt system with up to 67 sources, sample-rate down to 50 ns ? 8-channel interrupt-driven single-cycle data transfer facilities via peripheral event controller (pec), 24-b it pointers cover total address space ? clock generation via on-chip pll (factors 1:0.15 1:10), or via prescaler (factors 1:1 60:1) ? on-chip memory modules ? 2 kbytes on-chip dual-port ram (dpram) ? 2 kbytes on-chip data sram (dsram) ? 2 kbytes on-chip program/data sram (psram) ? up to 128 kbytes on-chip program memory (flash memory) ? on-chip peripheral modules ? 14-channel a/d converter with programmable resolution (10-bit or 8-bit) and conversion time (down to 2.55 s or 2.15 s) ? two 16-channel general purpose capture/compare units (12 input/output pins) ? capture/compare unit for flexible pwm signal generation (capcom6) (3/6 capture/compare channels and 1 compare channel) ? multi-functional general purpose timer unit with 5 timers ? two synchronous/asynchronous serial channels (usarts) ? two high-speed-synchronous serial channels ? on-chip real time clock ? idle, sleep, and power down modes with flexible power management ? programmable watchdog timer and oscillator watchdog ? up to 12 mbytes external address space for code and data ? programmable external bus characteristics for different address ranges ? multiplexed or demultiplexed external address/data buses ? selectable address bus width ? 16-bit or 8-bit data bus width ? four programmable chip-select signals ? up to 79 general purpose i/o lines, partly with selectable input thresholds and hysteresis
xc164s derivatives summary of features data sheet 3 v1.0, 2005-01 ? on-chip bootstrap loader ? supported by a large range of development tools like c-compilers, macro-assembler packages, emulators, evaluation boards, hll-debuggers, simulators, logic analyzer disassemblers, programming boards ? on-chip debug support via jtag interface ? 100-pin tqfp package, 0.5 mm (19.7 mil) pitch ordering information the ordering code for infineon microcontrollers provides an exact reference to the required product. this ordering code identifies: ? the derivative itself, i.e. its function set, the temperature range, and the supply voltage ? the package and the type of delivery. for the available ordering codes for the xc164s please refer to the ?product catalog microcontrollers? , which summarizes all available microcontroller variants. this document describes several derivatives of the xc164 group. table 1 enumerates these derivatives and summarizes the differences. as this document refers to all of these derivatives, some descriptions may not apply to a specific product. for simplicity all versions are referred to by the term xc164s throughout this document.
xc164s derivatives summary of features data sheet 4 v1.0, 2005-01 table 1 xc164s derivative synopsis derivative 1) program memory on-chip ram inter- faces clock saf-xc164s-16f40f 128 kbytes flash 2kbytes dpram, 2kbytes dsram, 2kbytes psram asc0, asc1, ssc0, ssc1 40 mhz SAF-XC164S-16F20F 128 kbytes flash 2kbytes dpram, 2kbytes dsram, 2kbytes psram asc0, asc1, ssc0, ssc1 20 mhz saf-xc164s-8f40f 64 kbytes flash 2kbytes dpram, 2kbytes dsram, 2kbytes psram asc0, asc1, ssc0, ssc1 40 mhz saf-xc164s-8f20f 64 kbytes flash 2kbytes dpram, 2kbytes dsram, 2kbytes psram asc0, asc1, ssc0, ssc1 20 mhz 1) this data sheet is valid for devices starting with and including design step ba.
xc164s derivatives general device information data sheet 5 v1.0, 2005-01 2 general devi ce information 2.1 introduction the xc164s derivatives are high-performance members of the infineon xc166 family of full featured single-chip cmos microcontrollers. these devices extend the functionality and performance of the c166 family in terms of instructions (mac unit), peripherals, and speed. they combine high cpu performance (up to 40 million instructions per second) with high peripheral functionality and enhanced io-capabilities. they also provide clock generation via pll and various on-chip memory modules such as program flash, program ram, and data ram. figure 1 logic symbol xc164s nmi rstout ea rstin ale rd wr /wrl v ddi/p v ssi/p port0 16 bit port1 16 bit port 3 14 bit port 4 8 bit port 5 14 bit xtal2 xtal1 port 9 6 bit v aref v agnd trst jtag debug port 20 5 bit via port 3
xc164s derivatives general device information data sheet 6 v1.0, 2005-01 2.2 pin configuration and definition the pins of the xc164s are described in detail in table 2 , including all their alternate functions. figure 2 summarizes all pins in a condensed way, showing their location on the 4 sides of the package. e*) marks pins to be used as alternate external interrupt inputs. figure 2 pin configuration (top view) xtal1 xtal2 v ssi v ddi p1h.7/a15/cc27/ex7in p1h.6/a14/cc26/ex6in p1h.5/a13/cc25/ex5in p1h.4/a12/cc24/ex4in p1h.3/a11/t7in/sclk1/ex3in/e* ) p1h.2/a10/c6p2 /mtsr1/ex2in p1h.1/a9/c 6p1 /mrst1/ex1in p1h.0/a8/c6p0 /cc23/ex0in v ssp v ddp p1l.7/a7/ c trap /cc22 p1l.6/a6/cout63 p1l.5/a5/cout62 p1l.4/a4/cc62 p1l.3/a3/cout61 p1l.2/a2/cc61 p1l.1/a1/cout60 p1l.0/a0/cc60 p0h.7/ad15 p0h.6/ad14 p0h.5/ad13 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 xc164s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p0h.4/ad12 p0l.7/ad7 p0l.6/ad6 p0l.5/ad5 p0l.4/ad4 p0l.3/ad3 p0l.2/ad2 p0l.1/ad1 p0l.0/ad0 p20.5/ea p20.4/ale p20.1/wr /wrl p20.0/rd v ssp v ddp p4.7/a23 p4.6/a22 p4.5/a21 p4.4/a20 p4.3/a19/cs0 p4.2/a18/cs1 p4.1/a17/cs2 p4.0/a16/cs3 p3.15/clkout/fo p3.13/sclk0/e*) rstin p20.12/ rstout nmi p0h.0/ad8 p0h.1/ad9 p0h.2/ad10 p0h.3/ad11 v ssp v ddp p9.0/cc16io p9.1/cc17io p9.2/cc18io p9.3/cc19io p9.4/cc20io p9.5/cc21io v ssp v ddp p5.0/an0 p5.1/an1 p5.2/an2 p5.3/an3 p5.4/an4 p5.5/an5 p5.10/an10/t6eud p5.11/an11/t5eud p5.6/an6 p5.7/an7 v aref v agnd p5.12/an12/t6in p5.13/an13/t5in p5.14/an14/t4eud p5.15/an15/t2eud v ssi v ddi trst v ssp v ddp p3.1/t6out/rxd1/tck/e*) p3.2/capin/tdi p3.3/t3out/tdo p3.4/t3eud/tms p3.5/t4in/txd1/brkout p3.6/t3in p3.7/t2in/brkin p3.8/mrst0 p3.9/mtsr0 p3.10/txd0/e*) p3.11/rxd0/e*) p3.12/bhe /wrh /e*)
xc164s derivatives general device information data sheet 7 v1.0, 2005-01 table 2 pin definitions and functions symbo l pin num. input outp. function rstin 1 i reset input with schmitt-trigger characteristics. a low level at this pin while the oscillator is running resets the xc164s. a spike filter suppresses input pulses <10 ns. input pulses >100 ns safely pass the filter. the minimum duration for a safe recognition should be 100 ns + 2 cpu clock cycles. note: the reset duration must be sufficient to let the hardware configuration signals settle. external circuitry must guarantee low level at the rstin pin at least until both power supply voltages have reached the operating range. p20.12 2 io for details, please refer to the description of p20 . nmi 3 i non-maskable interrupt input. a high to low transition at this pin causes the cpu to vector to the nmi trap routine. when the pwrdn (power down) instruction is executed, the nmi pin must be low in order to force the xc164s into power down mode. if nmi is high, when pwrdn is executed, the part will continue to run in normal mode. if not used, pin nmi should be pulled high externally. p0h.0- p0h.3 4 7 io for details, please refer to the description of port0 .
xc164s derivatives general device information data sheet 8 v1.0, 2005-01 p9 p9.0 p9.1 p9.2 p9.3 p9.4 p9.5 10 11 12 13 14 15 io i/o i i/o i i/o i i/o i i/o i/o port 9 is a 6-bit bidirectional i/o port. each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). the input threshold of port 9 is selectable (standard or special). the following port 9 pins also serve for alternate functions: cc16io capcom2: cc16 capture inp./compare outp., ex7in fast external interrupt 7 input (alternate pin b) cc17io capcom2: cc17 capture inp./compare outp., ex6in fast external interrupt 6 input (alternate pin b) cc18io capcom2: cc18 capture inp./compare outp., ex7in fast external interrupt 7 input (alternate pin a) cc19io capcom2: cc19 capture inp./compare outp., ex6in fast external interrupt 6 input (alternate pin a) cc20io capcom2: cc20 capture inp./compare outp. cc21io capcom2: cc21 capture inp./compare outp. p5 p5.0 p5.1 p5.2 p5.3 p5.4 p5.5 p5.10 p5.11 p5.6 p5.7 p5.12 p5.13 p5.14 p5.15 18 19 20 21 22 23 24 25 26 27 30 31 32 33 i i i i i i i i i i i i i i i port 5 is a 14-bit input-only port. the pins of port 5 also serve as analog input channels for the a/d converter, or they serve as timer inputs: an0 an1 an2 an3 an4 an5 an10, t6eud gpt2 timer t6 ext. up/down ctrl. inp. an11, t5eud gpt2 timer t5 ext. up/down ctrl. inp. an6 an7 an12, t6in gpt2 timer t6 count/gate input an13, t5in gpt2 timer t5 count/gate input an14, t4eud gpt1 timer t4 ext. up/down ctrl. inp. an15, t2eud gpt1 timer t2 ext. up/down ctrl. inp. table 2 pin definitions and functions (cont?d) symbo l pin num. input outp. function
xc164s derivatives general device information data sheet 9 v1.0, 2005-01 trst 36 i test-system reset input. a high level at this pin activates the xc164s?s debug system. for normal system operation, pin trst should be held low. p3 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p3.8 p3.9 p3.10 p3.11 p3.12 p3.13 p3.15 39 40 41 42 43 44 45 46 47 48 49 50 51 52 io o i/o i i i i o o i i i o o i i i i/o i/o o i i/o i o o i i/o i o o port 3 is a 14-bit bidirectional i/o port. each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). the input threshold of port 3 is selectable (standard or special). the following port 3 pins also serve for alternate functions: t6out gpt2 timer t6 toggle latch output, rxd1 asc1 data input (async.) or inp./outp. (sync.), ex1in fast external interrupt 1 input (alternate pin a), tck debug system: jtag clock input capin gpt2 register caprel capture input, tdi debug system: jtag data in t3out gpt1 timer t3 toggle latch output, tdo debug system: jtag data out t3eud gpt1 timer t3 external up/down control input, tms debug system: jtag test mode selection t4in gpt1 timer t4 count/gate/reload/capture inp txd1 asc0 clock/data output (async./sync.), b rkout debug system: break out t3in gpt1 timer t3 count/gate input t2in gpt1 timer t2 count/gate/reload/capture inp b rkin debug system: break in mrst0 ssc0 master-receive/slave-transmit in/out. mtsr0 ssc0 master-transmit/slave-receive out/in. txd0 asc0 clock/data output (async./sync.), ex2in fast external interrupt 2 input (alternate pin b) rxd0 asc0 data input (async.) or inp./outp. (sync.), ex2in fast external interrupt 2 input (alternate pin a) bhe external memory high byte enable signal, w rh external memory high byte write strobe, ex3in fast external interrupt 3 input (alternate pin b) sclk0 ssc0 master clock output / slave clock input., ex3in fast external interrupt 3 input (alternate pin a) clkout system clock output (=cpu clock), fout programmable frequency output table 2 pin definitions and functions (cont?d) symbo l pin num. input outp. function
xc164s derivatives general device information data sheet 10 v1.0, 2005-01 p4 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 53 54 55 56 57 58 59 60 io o o o o o o o o o i o i o i o i port 4 is an 8-bit bidirectional i/o port. each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). the input threshold of port 4 is selectable (standard or special). port 4 can be used to output the segment address lines, the optional chip select lines, and for serial interface lines: a16 least significant segment address line, c s3 chip select 3 output a17 segment address line, c s2 chip select 2 output a18 segment address line, c s1 chip select 1 output a19 segment address line, c s0 chip select 0 output a20 segment address line, ex5in fast external interrupt 5 input (alternate pin b) a21 segment address line, ex4in fast external interrupt 4 input (alternate pin b) a22 segment address line, ex5in fast external interrupt 5 input (alternate pin a) a23 most significant segment address line, ex4in fast external interrupt 4 input (alternate pin a) table 2 pin definitions and functions (cont?d) symbo l pin num. input outp. function
xc164s derivatives general device information data sheet 11 v1.0, 2005-01 p20 p20.0 p20.1 p20.4 p20.5 p20.12 63 64 65 66 2 io o o o i o port 20 is a 5-bit bidirectional i/o port. each pin can be programmed for input (output driver in high-impedance state) or output. the input threshold of port 20 is selectable (standard or special). the following port 20 pins also serve for alternate functions: rd external memory read strobe, activated for every external instruction or data read access. wr /wrl external memory write strobe. in wr -mode this pin is activated for every external data write access. in wrl -mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. ale address latch enable output. can be used for latching the address into external memory or an address latch in the multiplexed bus modes. ea external access enable pin. a low level at this pin during and after reset forces the xc164s to latch the configuration from port0 and pin rd , and to begin instruction execution out of external memory. a high level forces the xc164s to latch the configuration from pins rd , ale, and wr , and to begin instruction execution out of the internal program memory. "romless" versions must have this pin tied to ?0?. rstout internal reset indication output. is activated asynchronously with an external hardware reset. it may also be activated (selectable) synchronously with an internal software or watchdog reset. is deactivated upon the execution of the einit instruction, optionally at the end of reset, or at any time (before einit) via user software. note: port 20 pins may input configuration values (see ea ). table 2 pin definitions and functions (cont?d) symbo l pin num. input outp. function
xc164s derivatives general device information data sheet 12 v1.0, 2005-01 port0 p0l.0 - p0l.7 p0h.0 - p0l.3 p0h.4 - p0l.7 67 - 74 4 - 7 75 - 78 io port0 consists of the two 8-bit bidirectional i/o ports p0l and p0h. each pin can be programmed for input (output driver in high-impedance state) or output. in case of an external bus configuration, port0 serves as the address (a) and address/data (ad) bus in multiplexed bus modes and as the data (d) bus in demultiplexed bus modes. demultiplexed bus modes: data path width: 8-bit 16-bit p0l.0 ? p0l.7: d0 ? d7 d0 - d7 p0h.0 ? p0h.7: i/o d8 - d15 multiplexed bus modes: data path width: 8-bit 16-bit p0l.0 ? p0l.7: ad0 ? ad7 ad0 - ad7 p0h.0 ? p0h.7: a8 - a15 ad8 - ad15 note: at the end of an external reset (ea = 0) port0 also may input configuration values port1 p1l.0 p1l.1 p1l.2 p1l.3 p1l.4 p1l.5 p1l.6 p1l.7 p1h 79 80 81 82 83 84 85 86 io i/o o i/o o i/o o o i i/o port1 consists of the two 8-bit bidirectional i/o ports p1l and p1h. each pin can be programmed for input (output driver in high-impedance state) or output. port1 is used as the 16-bit address bus (a) in demultiplexed bus modes (also after switching from a demultiplexed to a multiplexed bus mode). the following port1 pins also serve for alt. functions: cc60 capcom6: input / output of channel 0 cout60 capcom6: output of channel 0 cc61 capcom6: input / output of channel 1 cout61 capcom6: output of channel 1 cc62 capcom6: input / output of channel 2 cout62 capcom6: output of channel 2 cout63 output of 10-bit compare channel ctrap capcom6: trap input ctrap is an input pin with an internal pullup resistor. a low level on this pin switches the capcom6 compare outputs to the logic level defined by software (if enabled). cc22io capcom2: cc22 capture inp./compare outp. continued table 2 pin definitions and functions (cont?d) symbo l pin num. input outp. function
xc164s derivatives general device information data sheet 13 v1.0, 2005-01 port1 (cont?d) p1h.0 p1h.1 p1h.2 p1h.3 p1h.4 p1h.5 p1h.6 p1h.7 89 90 91 92 93 94 95 96 io i i i/o i i i/o i i i/o i i/o i i i/o i i/o i i/o i i/o i continued cc6pos0 capcom6: position 0 input, ex0in fast external interrupt 0 input (default pin), cc23io capcom2: cc23 capture inp./compare outp. cc6pos1 capcom6: position 1 input, ex1in fast external interrupt 1 input (default pin), mrst1 ssc1 master-receive/slave-transmit in/out. cc6pos2 capcom6: position 2 input, ex2in fast external interrupt 2 input (default pin), mtsr1 ssc1 master-transmit/slave-receive out/inp. t7in capcom2: timer t7 count input, sclk1 ssc1 master clock output / slave clock input, ex3in fast external interrupt 3 input (default pin), ex0in fast external interrupt 0 input (alternate pin a) cc24io capcom2: cc24 capture inp./compare outp., ex4in fast external interrupt 4 input (default pin) cc25io capcom2: cc25 capture inp./compare outp., ex5in fast external interrupt 5 input (default pin) cc26io capcom2: cc26 capture inp./compare outp., ex6in fast external interrupt 6 input (default pin) cc27io capcom2: cc27 capture inp./compare outp., ex7in fast external interrupt 7 input (default pin) xtal2 xtal1 99 100 o i xtal2: output of the oscillator amplifier circuit xtal1: input to the oscillator amplifier and input to the internal clock generator to clock the device from an external source, drive xtal1, while leaving xtal2 unconnected. minimum and maximum high/low and rise/fall times specified in the ac characteristics must be observed. v aref 28 - reference voltage for the a/d converter. v agnd 29 - reference ground for the a/d converter. v ddi 35, 97 - digital core supply voltage (on-chip modules): +2.5 v during normal operation and idle mode. please refer to the operating conditions table 2 pin definitions and functions (cont?d) symbo l pin num. input outp. function
xc164s derivatives general device information data sheet 14 v1.0, 2005-01 v ddp 9, 17, 38, 61, 87 - digital pad supply voltage (pin output drivers): +5 v during normal operation and idle mode. please refer to the operating conditions v ssi 34, 98 - digital ground. connect decoupling capacitors to adjacent v dd / v ss pin pairs as close as possible to the pins. all v ss pins must be connected to the ground-line or ground- plane. v ssp 8, 16, 37, 62, 88 - table 2 pin definitions and functions (cont?d) symbo l pin num. input outp. function
xc164s derivatives functional description data sheet 15 v1.0, 2005-01 3 functional description the architecture of the xc164s combines advantages of risc, cisc, and dsp processors with an advanced peripheral subsystem in a very well-balanced way. in addition, the on-chip memory blocks allow the design of compact systems-on-silicon with maximum performance (computing, control, communication). the on-chip memory blocks (program code- memory and sram, dual-port ram, data sram) and the set of generic peripherals are connected to the cpu via separate buses. another bus, the lxbus, connects additional on-chip resoures as well as external resources (see figure 3 ). this bus structure enhances the overall system performance by enabling the concurrent operation of several subsystems of the xc164s. the following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the xc164s. figure 3 block diagram interrupt bus xtal saf-xc164s-16fxxf ac osc / pll cl ock generati on rtc wdt gpt t2 t3 t4 t5 t6 ssc0 brgen (spi) asc1 brgen (usart) adc 8/10-bit 12/16 channels cc2 t7 t8 cc6 t12 t13 ebc xbus cont rol external bus cont rol progmem flash 128 kbytes p 20 14 port 5 16 psram dpram dsram c166sv2-core pm u dmu cpu asc0 brgen (usart) ssc1 brgen (spi) cc1 t0 t1 port1 port0 port 3 port 4 port 9 16 14 8 6 5 interrupt & pec pe r i ph e r al data bus ocds debug support
xc164s derivatives functional description data sheet 16 v1.0, 2005-01 3.1 memory subsystem and organization the memory space of the xc164s is configured in a von neumann architecture, which means that all internal and external resources, such as code memory, data memory, registers and i/o ports, are organized with in the same linear address space. this common memory space includes 16 mbytes and is arranged as 256 segments of 64 kbytes each, where each segment consists of four data pages of 16 kbytes each. the entire memory space can be accessed bytewise or wordwise. portions of the on- chip dpram and the register spaces (e/sfr) have additionally been made directly bitaddressable. the internal data memory areas and the special function register areas (sfr and esfr) are mapped into segment 0, the system segment. the program management unit (pmu) handles all code fetches and, therefore, controls accesses to the program memories, such as flash memory and psram. the data management unit (dmu) handles all data transfers and, therefore, controls accesses to the dsram and the on-chip peripherals. both units (pmu and dmu) are connected via the high-speed system bus to exchange data. this is required if operands are read from program memory, code or data is written to the psram, code is fetched from external memory, or data is read from or written to external resources, including peripherals on the lxbus. the system bus allows concurrent two-way communication for maximum transfer performance. up to 128 kbytes of on-chip flash memory store code or constant data. the on-chip flash memory is organized as four 8-kbyte sectors, one 32-kbyte sector, and one 64- kbyte sectors. each sector can be separately write protected 1) , erased and programmed (in blocks of 128 bytes). the complete flash area can be read-protected. a password sequence temporarily unlocks protected areas. the flash module combines very fast 64-bit one-cycle read accesses with protected and efficient writing algorithms for programming and erasing. thus, program execution out of the internal flash results in maximum performance. dynamic error correction provides extremely high read data security for all read accesses. programming typically takes 2 ms per 128-byte block (5 ms max.), erasing a sector typically takes 200 ms (500 ms max.). 2 kbytes of on-chip program sram (psram) are provided to store user code or data. the psram is accessed via the pmu and is therefore optimized for code fetches. 2 kbytes of on-chip data sram (dsram) are provided as a storage for general user data.the dsram is accessed via the dmu and is therefore optimized for data accesses. 2 kbytes of on-chip dual-port ram (dpram) are provided as a storage for user defined variables, for the system stack, gene ral purpose register banks. a register bank can consist of up to 16 wordwide (r0 to r15) and/or bytewide (rl0, rh0, ?, rl7, rh7) 1) each two 8-kbyte sectors are combined for write-protection purposes.
xc164s derivatives functional description data sheet 17 v1.0, 2005-01 so-called general purpose registers (gprs). the upper 256 bytes of the dpram are directly bitaddressable. when used by a gpr, any location in the dpram is bitaddressable. 1024 bytes (2 512 bytes) of the address space are reserved for the special function register areas (sfr space and esfr space) . sfrs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. unused sfr addresses are reserved for future members of the xc166 family. therefore, they should either not be accessed, or written with zeros, to ensure upward compatibility. in order to meet the needs of designs where more memory is required than is provided on chip, up to 12 mbytes (approximately, see table 3 ) of external ram and/or rom can be connected to the microcontroller. the external bus interface also provides access to external peripherals. table 3 xc164s memory map 1) 1) accesses to the shaded areas generate external bus accesses. address area start loc. end loc. area size 2) 2) the areas marked with ? xc164s derivatives functional description data sheet 18 v1.0, 2005-01 3.2 external bus controller all of the external memory accesses are performed by a particular on-chip external bus controller (ebc). it can be programmed either to single chip mode when no external memory is required, or to one of four different external memory access modes 1) , which are as follows: ?16 24-bit addresses, 16-bit data, demultiplexed ?16 24-bit addresses, 16-bit data, multiplexed ?16 24-bit addresses, 8-bit data, multiplexed ?16 24-bit addresses, 8-bit data, demultiplexed in the demultiplexed bus modes, addresses are output on port1 and data is input/output on port0 or p0l, respectively. in the multiplexed bus modes both addresses and data use port0 for input/output. the high order address (segment) lines use port 4. the number of active segment address lines is selectable, restricting the external address space to 8 mbytes 64 kbytes. this is required when interface lines are assigned to port 4. up to 4 external cs signals (3 windows plus default) can be generated in order to save external glue logic. external modules can directly be connected to the common address/data bus and their individual select lines. important timing characteristics of the external bus interface have been made programmable (via registers tconcsx/fconcsx) to allow the user the adaption of a wide range of different types of memories and external peripherals. in addition, up to 4 independent address windows may be defined (via registers addrselx) which control the access to different resources with different bus characteristics. these address windows are arranged hierarchically where window 4 overrides window 3, and window 2 overrides window 1. all accesses to locations not covered by these 4 address windows are controlled by tconcs0/fconcs0. the currently active window can generate a chip select signal. the external bus timing is related to the rising edge of the reference clock output clkout. the external bus protocol is compatible with that of the standard c166 family. the ebc also controls accesses to resources connected to the on-chip lxbus. the lxbus is an internal representation of the external bus and allows accessing integrated peripherals and modules in the same way as external components. 1) bus modes are switched dynamically if several address windows with different mode settings are used.
xc164s derivatives functional description data sheet 19 v1.0, 2005-01 3.3 central processing unit (cpu) the main core of the cpu consists of a 5-stage execution pipeline with a 2-stage instruction-fetch pipeline, a 16-bit arithmetic and logic unit (alu), a 32-bit/40-bit multiply and accumulate unit (mac), a register-file providing three register banks, and dedicated sfrs. the alu features a multiply and divide unit, a bit-mask generator, and a barrel shifter. figure 4 cpu block diagram based on these hardware provisions, most of the xc164s?s instructions can be executed in just one machine cycle which requires 25 ns at 40 mhz cpu clock. for example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. also multiplication and most mac instructions execute in one single cycle. all multiple-cycle instructions have been optimized so that they can be executed very fast as well: for example, a 32-/16-bit division is started within 4 cycles, while the remaining 15 cycles are executed in the address data in data out csp ip cpucon1 cpucon2 fifo ifu idx0 idx1 qx1 qx0 qr1 qr0 sp spseg vecseg stkov stkun dpp0 dpp1 dpp3 dpp2 +/- +/- adu mdl mdh mal division unit mah multiply unit msw mcw alu rf +/- +/- zeros psw ones mrw tfr cpuid mdc barrel-shifter bit-mask-gen. multiply unit wb mac cpu buffer cp 2-stage prefetch pipeline 5-stage pipeline ipip dpram address data in data out dmu r15 r14 r0 r1 gprs r15 r14 r0 r1 gprs r15 r14 r0 r1 gprs r15 r14 r0 r1 gprs sram data in address data out peripheral-bus pmu internal program memory system-bus address data in data out system-bus prefetch unit branch unit return stack injection/exception handler
xc164s derivatives functional description data sheet 20 v1.0, 2005-01 background. another pipeline optimization, the branch target prediction, allows eliminating the execution time of branch instructions if the prediction was correct. the cpu has a register context consisting of up to three register banks with 16 wordwide gprs each at its disposal. one of these register banks is physically allocated within the on-chip dpram area. a context pointer (cp) register determines the base address of the active register bank to be accessed by the cpu at any time. the number of register banks is only restricted by the available internal ram space. for easy parameter passing, a register bank may overlap others. a system stack of up to 32 kwords is prov ided as a storage for temporary data. the system stack can be allocated to any location within the address space (preferably in the on-chip ram area), and it is accessed by th e cpu via the stack pointer (sp) register. two separate sfrs, stkov and stkun, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. the high performance offered by the hardware implementation of the cpu can efficiently be utilized by a programmer via the highly efficient xc164s instruction set which includes the following instruction classes: ? standard arithmetic instructions ? dsp-oriented arithmetic instructions ? logical instructions ? boolean bit manipulation instructions ? compare and loop control instructions ? shift and rotate instructions ? prioritize instruction ? data movement instructions ? system stack instructions ? jump and call instructions ? return instructions ? system control instructions ? miscellaneous instructions the basic instruction length is either 2 or 4 bytes. possible operand types are bits, bytes and words. a variety of direct, indirect or immediate addressing modes are provided to specify the required operands.
xc164s derivatives functional description data sheet 21 v1.0, 2005-01 3.4 interrupt system with an interrupt response time of typically 8 cpu clocks (in case of internal program execution), the xc164s is capable of reacting very fast to the occurrence of non- deterministic events. the architecture of the xc164s supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. any of these interrupt requests can be programmed to being serviced by the interrupt controller or by the peripheral event controller (pec). in contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ?stolen? from the current cpu activity to perform a pec service. a pec service implies a single byte or word data transfer between any two memory locations with an additional increment of either the pec source, or the destination pointer, or both. an individual pec transfer counter is implicitly decremented for each pec service except when performing in the continuous transfer mode. when this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. pec services are very well suited, for example, for supporting the transmission or reception of blocks of data. the xc164s has 8 pec channels each of which offers such fast interrupt-driven data transfer capabilities. a separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt nodes. via its related register, each node can be programmed to one of sixteen interrupt priority levels. once having been accepted by the cpu, an interrupt service can only be interrupted by a higher prioritized service request. for the standard interrupt processing, each of the possible interrupt nodes has a dedicated vector location. fast external interrupt inputs are provided to service external interrupts with high precision requirements. these fast in terrupt inputs feature programmable edge detection (rising edge, falling edge, or both edges). software interrupts are supported by means of the ?trap? instruction in combination with an individual trap (interrupt) number. table 4 shows all of the possible xc164s interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. note: interrupt nodes which are not assigned to peripherals (unassigned nodes), may be used to generate software controlled interrupt requests by setting the respective interrupt request bit (xir).
xc164s derivatives functional description data sheet 22 v1.0, 2005-01 table 4 xc164s interrupt nodes source of interrupt or pec service request control register vector location 1) trap number capcom register 0 cc1_cc0ic xx?0040 h 10 h / 16 d capcom register 1 cc1_cc1ic xx?0044 h 11 h / 17 d capcom register 2 cc1_cc2ic xx?0048 h 12 h / 18 d capcom register 3 cc1_cc3ic xx?004c h 13 h / 19 d capcom register 4 cc1_cc4ic xx?0050 h 14 h / 20 d capcom register 5 cc1_cc5ic xx?0054 h 15 h / 21 d capcom register 6 cc1_cc6ic xx?0058 h 16 h / 22 d capcom register 7 cc1_cc7ic xx?005c h 17 h / 23 d capcom register 8 cc1_cc8ic xx?0060 h 18 h / 24 d capcom register 9 cc1_cc9ic xx?0064 h 19 h / 25 d capcom register 10 cc1_cc10ic xx?0068 h 1a h / 26 d capcom register 11 cc1_cc11ic xx?006c h 1b h / 27 d capcom register 12 cc1_cc12ic xx?0070 h 1c h / 28 d capcom register 13 cc1_cc13ic xx?0074 h 1d h / 29 d capcom register 14 cc1_cc14ic xx?0078 h 1e h / 30 d capcom register 15 cc1_cc15ic xx?007c h 1f h / 31 d capcom register 16 cc2_cc16ic xx?00c0 h 30 h / 48 d capcom register 17 cc2_cc17ic xx?00c4 h 31 h / 49 d capcom register 18 cc2_cc18ic xx?00c8 h 32 h / 50 d capcom register 19 cc2_cc19ic xx?00cc h 33 h / 51 d capcom register 20 cc2_cc20ic xx?00d0 h 34 h / 52 d capcom register 21 cc2_cc21ic xx?00d4 h 35 h / 53 d capcom register 22 cc2_cc22ic xx?00d8 h 36 h / 54 d capcom register 23 cc2_cc23ic xx?00dc h 37 h / 55 d capcom register 24 cc2_cc24ic xx?00e0 h 38 h / 56 d capcom register 25 cc2_cc25ic xx?00e4 h 39 h / 57 d capcom register 26 cc2_cc26ic xx?00e8 h 3a h / 58 d capcom register 27 cc2_cc27ic xx?00ec h 3b h / 59 d capcom register 28 cc2_cc28ic xx?00e0 h 3c h / 60 d capcom register 29 cc2_cc29ic xx?0110 h 44 h / 68 d
xc164s derivatives functional description data sheet 23 v1.0, 2005-01 capcom register 30 cc2_cc30ic xx?0114 h 45 h / 69 d capcom register 31 cc2_cc31ic xx?0118 h 46 h / 70 d capcom timer 0 cc1_t0ic xx?0080 h 20 h / 32 d capcom timer 1 cc1_t1ic xx?0084 h 21 h / 33 d capcom timer 7 cc2_t7ic xx?00f4 h 3d h / 61 d capcom timer 8 cc2_t8ic xx?00f8 h 3e h / 62 d gpt1 timer 2 gpt12e_t2ic xx?0088 h 22 h / 34 d gpt1 timer 3 gpt12e_t3ic xx?008c h 23 h / 35 d gpt1 timer 4 gpt12e_t4ic xx?0090 h 24 h / 36 d gpt2 timer 5 gpt12e_t5ic xx?0094 h 25 h / 37 d gpt2 timer 6 gpt12e_t6ic xx?0098 h 26 h / 38 d gpt2 caprel reg. gpt12e_cric xx?009c h 27 h / 39 d a/d conversion compl. adc_cic xx?00a0 h 28 h / 40 d a/d overrun error adc_eic xx?00a4 h 29 h / 41 d asc0 transmit asc0_tic xx?00a8 h 2a h / 42 d asc0 transmit buffer asc0_tbic xx?011c h 47 h / 71 d asc0 receive asc0_ric xx?00ac h 2b h / 43 d asc0 error asc0_eic xx?00b0 h 2c h / 44 d asc0 autobaud asc0_abic xx?017c h 5f h / 95 d ssc0 transmit ssc0_tic xx?00b4 h 2d h / 45 d ssc0 receive ssc0_ric xx?00b8 h 2e h / 46 d ssc0 error ssc0_eic xx?00bc h 2f h / 47 d pll/owd pllic xx?010c h 43 h / 67 d asc1 transmit 2) asc1_tic xx?0120 h 48 h / 72 d asc1 transmit buffer asc1_tbic xx?0178 h 5e h / 94 d asc1 receive asc1_ric xx?0124 h 49 h / 73 d asc1 error asc1_eic xx?0128 h 4a h / 74 d asc1 autobaud asc1_abic xx?0108 h 42 h / 66 d end of pec subch. eopic xx?0130 h 4c h / 76 d capcom6 timer t12 ccu6_t12ic xx?0134 h 4d h / 77 d table 4 xc164s interrupt nodes (cont?d) source of interrupt or pec service request control register vector location 1) trap number
xc164s derivatives functional description data sheet 24 v1.0, 2005-01 capcom6 timer t13 ccu6_t13ic xx?0138 h 4e h / 78 d capcom6 emergency ccu6_eic xx?013c h 4f h / 79 d capcom6 ccu6_ic xx?0140 h 50 h / 80 d ssc1 transmit ssc1_tic xx?0144 h 51 h / 81 d ssc1 receive ssc1_ric xx?0148 h 52 h / 82 d ssc1 error ssc1_eic xx?014c h 53 h / 83 d unassigned node --- xx?0150 h 54 h / 84 d unassigned node --- xx?0154 h 55 h / 85 d unassigned node --- xx?0158 h 56 h / 86 d unassigned node --- xx?015c h 57 h / 87 d unassigned node --- xx?0164 h 59 h / 89 d unassigned node --- xx?0168 h 5a h / 90 d unassigned node --- xx?016c h 5b h / 91 d unassigned node --- xx?0170 h 5c h / 92 d rtc rtc_ic xx?0174 h 5d h / 93 d unassigned node --- xx?0100 h 40 h / 64 d unassigned node --- xx?0104 h 41 h / 65 d unassigned node --- xx?012c h 4b h / 75 d unassigned node --- xx?00fc h 3f h / 63 d unassigned node --- xx?0160 h 58 h / 88 d 1) register vecseg defines the segment where the vector table is located to. bitfield vecsc in register cpucon1 defines the distance between two adjacent vectors. this table represents the default setting, with a distance of 4 (two words) between two vectors. 2) the interrupt nodes assigned to asc1 are only available in derivatives including the asc1. otherwise, they are unassigned nodes. table 4 xc164s interrupt nodes (cont?d) source of interrupt or pec service request control register vector location 1) trap number
xc164s derivatives functional description data sheet 25 v1.0, 2005-01 the xc164s also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ?hardware traps?. hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). the occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (tfr). except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. in turn, hardware trap services can normally not be interrupted by standard or pec interrupts. table 5 shows all of the possible exceptions or error conditions that can arise during run- time: table 5 hardware trap summary exception condition trap flag trap vector vector location 1) 1) register vecseg defines the segment where the vector table is located to. trap number trap priority reset functions: ? hardware reset ? software reset ? w-dog timer overflow ? reset reset reset xx?0000 h xx?0000 h xx?0000 h 00 h 00 h 00 h iii iii iii class a hardware traps: ? non-maskable interrupt ? stack overflow ? stack underflow ? software break nmi stkof stkuf softbrk nmitrap stotrap stutrap sbrktrap xx?0008 h xx?0010 h xx?0018 h xx?0020 h 02 h 04 h 06 h 08 h ii ii ii ii class b hardware traps: ? undefined opcode ? pmi access error ? protected instruction fault ? illegal word operand access undopc pacer prtflt illopa btrap btrap btrap btrap xx?0028 h xx?0028 h xx?0028 h xx?0028 h 0a h 0a h 0a h 0a h i i i i reserved ? ? [2c h ? 3c h ] [0b h ? 0f h ] ? software traps ? trap instruction ?? any [xx?0000 h ? xx?01fc h ] in steps of 4 h any [00 h ? 7f h ] current cpu priority
xc164s derivatives functional description data sheet 26 v1.0, 2005-01 3.5 on-chip debug support (ocds) the on-chip debug support system provid es a broad range of debug and emulation features built into the xc164s. the user software running on the xc164s can thus be debugged within the target system environment. the ocds is controlled by an external debugging device via the debug interface, consisting of the ieee-1149-conforming jtag port and a break interface. the debugger controls the ocds via a set of dedicated registers accessible via the jtag interface. additionally, the ocds system can be controlled by the cpu, e.g. by a monitor program. an injection interface allows the execution of ocds-generated instructions by the cpu. multiple breakpoints can be triggered by on -chip hardware, by software, or by an external trigger input. single stepping is su pported as well as the injection of arbitrary instructions and read/write access to the complete internal address space. a breakpoint trigger can be answered with a cpu-halt, a monitor call, a data transfer, or/and the activation of an external signal. tracing data can be obtained via the jtag interface or via the external bus interface for increased performance. the debug interface uses a set of 6 interface signals (4 jtag lines, 2 break lines) to communicate with external circuitry. these interface signals are realized as alternate functions on port 3 pins. complete system emulation is supported by the new emulation technology (net) interface. via this full-featured emulation interface (including internal buses, control, status, and pad signals) the xc164s chip can be connected to a net carrier chip. the use of the xc164s production chip together with the carrier chip provides superior emulation behavior, because the emulation system shows exactly the same functionality as the production chip (use of the identical silicon).
xc164s derivatives functional description data sheet 27 v1.0, 2005-01 3.6 capture/compare units (capcom1/2) the capcom units support generation and control of timing sequences on up to 32 channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered mode). the capcom units are typically used to handle high speed i/o tasks such as pulse and waveform generation, pulse width modulation (pmw), digital to analog (d/a) conversion, software timing, or time recording relative to external events. four 16-bit timers (t0/t1, t7/t8) with reload registers provide two independent time bases for each capture/compare register array. the input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer t6 in module gpt2. this provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. in addition, external count inputs for capcom timers t0 and t7 allow event scheduling for the capture/compare registers relative to external events. both of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either capcom timer t0 or t1 (t7 or t8, respectively), and programmed for capture or compare function. 12 registers of the capcom2 module have each one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. table 6 compare modes (capcom1/2) compare modes function mode 0 interrupt-only compare mode; several compare interrupts per timer period are possible mode 1 pin toggles on each compare match; several compare events per timer period are possible mode 2 interrupt-only compare mode; only one compare interrupt per timer period is generated mode 3 pin set ?1? on match; pin reset ?0? on compare timer overflow; only one compare event per timer period is generated double register mode two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible single event mode generates single edges or pulses; can be used with any compare mode
xc164s derivatives functional description data sheet 28 v1.0, 2005-01 when a capture/compare register has bee n selected for capture mode, the current contents of the allocated timer will be latched (?captured?) into the capture/compare register in response to an external event at the port pin which is associated with this register. in addition, a specific interrupt request for this capture/compare register is generated. either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. the contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. when a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode.
xc164s derivatives functional description data sheet 29 v1.0, 2005-01 figure 5 capcom1/2 unit block diagram sixteen 16-bit capture/ compare registers mode control (capture or compare) t0/t7 input control t1/t8 input control mcb05569 ccxirq ccxirq ccxirq capcom1 provides channels x = 0 ? 15, capcom2 provides channels x = 16 ? 31. (see signals ccxio and ccxirq) t0irq, t7irq t1irq, t8irq ccxio ccxio ccxio t0in/t7in t6ouf f cc t6ouf f cc reload reg. t0rel/t7rel timer t0/t7 timer t1/t8 reload reg. t1rel/t8rel
xc164s derivatives functional description data sheet 30 v1.0, 2005-01 3.7 the capture/compare unit capcom6 the capcom6 unit supports generation and control of timing sequences on up to three 16-bit capture/compare channels plus one independent 10-bit compare channel. in compare mode the capcom6 unit provides two output signals per channel which have inverted polarity and non-overlapping pulse transitions (deadtime control). the compare channel can generate a single pwm output signal and is further used to modulate the capture/compare output signals. in capture mode the contents of compare timer t12 is stored in the capture registers upon a signal transition at pins ccx. compare timers t12 (16-bit) and t13 (10-bit) are free running timers which are clocked by the prescaled system clock. figure 6 capcom6 block diagram for motor control applications both subunits may generate versatile multichannel pwm signals which are basically either controlled by compare timer t12 or by a typical hall sensor pattern at the interrupt inputs (block commutation). control cc channel 0 cc60 cc channel 1 cc61 cc channel 2 cc62 mcb04109 prescaler offset register t12of compare timer t12 16-bit period register t12p mode select register cc6msel trap register port control logic cntrol register ctcon compare register cmp13 prescaler compare timer t13 10-bit period register t13p block commutation control cc6mcon.h cc60 cout60 cc61 cout61 cc62 cout62 ctrap cc6pos0 cc6pos1 cc6pos2 f cpu f cpu cout63 the timer registers (t12, t13) are not directly accessible. the period and offset registers are loading a value into the timer registers.
xc164s derivatives functional description data sheet 31 v1.0, 2005-01 3.8 general purpose timer (gpt12e) unit the gpt12e unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. the gpt12e unit incorporates five 16-bit timers which are organized in two separate modules, gpt1 and gpt2. each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. each of the three timers t2, t3, t4 of module gpt1 can be configured individually for one of four basic modes of operation, which are timer, gated timer, counter, and incremental interface mode. in timer mode, the input clock for a timer is derived from the system clock, divided by a programmable prescaler, while counter mode allows a timer to be clocked in reference to external events. pulse width or duty cycle measurement is supported in gated timer mode, where the operation of a timer is controlled by the ?gate? level on an external input pin. for these purposes, each timer has one associated port pin (txin) which serves as gate or clock input. the maximum resolution of the timers in module gpt1 is 4 system clock cycles. the count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (txeud) to facilitate e.g. position tracking. in incremental interface mode the gpt1 timers (t2, t3, t4) can be directly connected to the incremental position sensor signals a and b via their respective inputs txin and txeud. direction and count signals are internally derived from these two input signals, so the contents of the respective timer tx corresponds to the sensor position. the third position sensor signal top0 can be connected to an interrupt input. timer t3 has an output toggle latch (t3otl) which changes its state on each timer over- flow/underflow. the state of this latch may be output on pin t3out e.g. for time out monitoring of external hardware components. it may also be used internally to clock timers t2 and t4 for measuring long time periods with high resolution. in addition to their basic operating modes, timers t2 and t4 may be configured as reload or capture registers for timer t3. when used as capture or reload registers, timers t2 and t4 are stopped. the contents of timer t3 is captured into t2 or t4 in response to a signal at their associated input pins (txin). timer t3 is reloaded with the contents of t2 or t4 triggered either by an external signal or by a selectable state transition of its toggle latch t3otl. when both t2 and t4 are configured to alternately reload t3 on opposite state transitions of t3otl with the low and high times of a pwm signal, this signal can be constantly generated without software intervention.
xc164s derivatives functional description data sheet 32 v1.0, 2005-01 figure 7 block diagram of gpt1 with its maximum resolution of 2 system clock cycles, the gpt2 module provides precise event control and time measurement. it includes two timers (t5, t6) and a capture/reload register (caprel). both timers can be clocked with an input clock which is derived from the cpu clock via a programmable prescaler or with external signals. the count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (txeud). concatenation of the timers is supported via the output toggle latch (t6otl) of timer t6, which changes its state on each timer overflow/underflow. the state of this latch may be used to clock timer t5, and/or it may be output on pin t6out. the overflows/underflows of timer t6 can additionally be used to clock the capcom1/2 timers, and to cause a reload from the caprel register. the caprel register may capture the contents of timer t5 based on an external signal transition on the corresponding port pin (capin), and timer t5 may optionally be cleared t3 mode control 2 n : 1 f sys 2 n : 1 f sys t2 mode control gpt1 timer t2 reload capture 2 n : 1 f sys t4 mode control gpt1 timer t4 reload capture gpt1 timer t3 t3otl u/d t2eud t2in t3in t3eud t4in t4eud toggle ff u/d u/d interrupt request (t2ir) interrupt request (t3ir) interrupt request (t4ir) mct04825_xc.vsd t6out n = 2 ? 12
xc164s derivatives functional description data sheet 33 v1.0, 2005-01 after the capture procedure. this allows the xc164s to measure absolute time differences or to perform pulse multiplication without software overhead. the capture trigger (timer t5 to caprel) may also be generated upon transitions of gpt1 timer t3?s inputs t3in and/or t3eud. this is especially advantageous when t3 operates in incremental interface mode. figure 8 block diagram of gpt2 mux 2 n : 1 f sys t5 mode control gpt2 timer t5 2 n : 1 f sys t6 mode control gpt2 timer t6 gpt2 caprel t6otl t5eud t5in t3in/ t3eud capin t6in t6eud t6out u/d u/d interrupt request (t5ir) interrupt request (crir) interrupt request (t6ir) other modules clear capture ct3 mcb03999_xc.vsd toggle ff clear n = 1 ? 11
xc164s derivatives functional description data sheet 34 v1.0, 2005-01 3.9 real time clock the real time clock (rtc) module of the xc164s is directly clocked via a separate clock driver with the prescaled on-chip oscillator frequency ( f rtc = f osc / 32). it is therefore independent from the selected clock generation mode of the xc164s. the rtc basically consists of a chain of divider blocks: ? a selectable 8:1 divider (on - off) ? the reloadable 16-bit timer t14 ? the 32-bit rtc timer block (accessible via registers rtch and rtcl), made of: ? a reloadable 10-bit timer ? a reloadable 6-bit timer ? a reloadable 6-bit timer ? a reloadable 10-bit timer all timers count up. each timer can generate an interrupt request. all requests are combined to a common node request. figure 9 rtc block diagram note: the registers associated with the rt c are not affected by a reset in order to maintain the correct system time even when intermediate resets are executed. mcb04805_xc.vsd t14rel t14 t14-register cnt-register rel-register 10 bits 6 bits 6 bits 10 bits 10 bits 6 bits 6 bits 10 bits interrupt sub node cnt in t0 cnt int1 cnt in t2 cnt int3 rtcint 1 0 8 run pre f rtc mux
xc164s derivatives functional description data sheet 35 v1.0, 2005-01 the rtc module can be used for different purposes: ? system clock to determine the current time and date, optionally during idle mode, sleep mode, and power down mode ? cyclic time based interrupt, to provide a system time tick independent of cpu frequency and other resources, e.g. to wake up regularly from idle mode. ? 48-bit timer for long term measurements (maximum timespan is >100 years). ? alarm interrupt for wake-up on a defined time
xc164s derivatives functional description data sheet 36 v1.0, 2005-01 3.10 a/d converter for analog signal measurement, a 10-bit a/d converter with 14 multiplexed input channels and a sample and hold circuit has been integrated on-chip. it uses the method of successive approximation. the sample time (for loading the capacitors) and the conversion time is programmable (in two modes) and can thus be adjusted to the external circuitry. the a/d converter can al so operate in 8-bit conversion mode, where the conversion time is further reduced. overrun error detection/protection is provided for the conversion result register (addat): either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended in such a case until the previous result has been read. for applications which require less analog input channels, the remaining channel inputs can be used as digital input port pins. the a/d converter of the xc164s supports four different conversion modes. in the standard single channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. in the single channel continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. in the auto scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. in the auto scan continuous mode, the prespecified channels are repeatedly sampled and converted. in addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence. this is called channel injection mode. the peripheral event controller (pec) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. after each reset and also during normal operation the adc automatically performs calibration cycles. this automatic self-calibration constantly adjusts the converter to changing operating conditions (e.g. temperature) and compensates process variations. these calibration cycles are part of the conversion cycle, so they do not affect the normal operation of the a/d converter. in order to decouple analog inputs from digital noise and to avoid input trigger noise those pins used for analog input can be disconnected from the digital io or input stages under software control. this can be selected for each pin separately via register p5didis (port 5 digital input disable). the auto-power-down feature of the a/d converter minimizes the power consumption when no conversion is in progress.
xc164s derivatives functional description data sheet 37 v1.0, 2005-01 3.11 asynchronous/synchronous serial interfaces (asc0/asc1) the asynchronous/synchronous serial interfaces asc0/asc1 (usarts) provide serial communication with other microcontrollers, processors, terminals or external peripheral components. they are upward compatible with the serial ports of the infineon 8-bit microcontroller families and support full-duplex asynchronous communication and half- duplex synchronous communication. a dedicated baud rate generator with a fractional divider precisely generates all standard baud rates without oscillator tuning. for transmission, reception, error handling, and baudrate detection 5 separate interrupt vectors are provided. in asynchronous mode, 8- or 9-bit data fram es (with optional parity bit) are transmitted or received, preceded by a start bit and terminated by one or two stop bits. for multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake-up bit mode). irda data transmissions up to 115.2 kbit/s with fixed or programmable irda pulse width are supported. in synchronous mode, bytes (8 bits) are transmitted or received synchronously to a shift clock which is generated by the asc0/1. the lsb is always shifted first. in both modes, transmission and reception of data is fifo-buffered. an autobaud detection unit allows to detect asynchronous data frames with its baudrate and mode with automatic initialization of the baudrate generator and the mode control bits. a number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. a parity bit can automatically be generated on transmission or be checked on reception. framing error detection allows to recognize data frames with missing stop bits. an overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. summary of features ? full-duplex asynchronous operating modes ? 8- or 9-bit data frames, lsb first, one or two stop bits, parity generation/checking ? baudrate from 2.5 mbit/s to 0.6 bit/s (@ 40 mhz) ? multiprocessor mode for automatic address/data byte detection ? support for irda data transmission/reception up to max. 115.2 kbit/s (@ 40 mhz) ? loop-back capability ? auto baudrate detection ? half-duplex 8-bit synchronous operating mode at 5 mbit/s to 406.9 bit/s (@ 40 mhz) ? buffered transmitter/receiver with fifo support (8 entries per direction) ? loop-back option available for testing purposes ? interrupt generation on transmitter buffer empty condition, last bit transmitted condition, receive buffer full condition, error condition (frame, parity, overrun error), start and end of an autobaud detection
xc164s derivatives functional description data sheet 38 v1.0, 2005-01 3.12 high speed synchronous serial channels (ssc0/ssc1) the high speed synchronous serial channels ssc0/ssc1 support full-duplex and half- duplex synchronous communication. it may be configured so it interfaces with serially linked peripheral components, full spi functionality is supported. a dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. for transmission, reception and error handling three separate interrupt vectors are provided. the ssc transmits or receives characters of 2 ? 16 bits length synchronously to a shift clock which can be generated by the ssc (master mode) or by an external master (slave mode). the ssc can start shifting with the lsb or with the msb and allows the selection of shifting and latching clock edges as well as the clock polarity. a number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. transmit error and receive error supervise the correct handling of the data buffer. phase error and baudrate error detect incorrect serial data. summary of features ? master or slave mode operation ? full-duplex or half-duplex transfers ? baudrate generation from 20 mbit/s to 305.18 bit/s (@ 40 mhz) ? flexible data format ? programmable number of data bits: 2 to 16 bits ? programmable shift direction: lsb-first or msb-first ? programmable clock polarity: idle low or idle high ? programmable clock/data phase: data shift with leading or trailing clock edge ? loop back option available for testing purposes ? interrupt generation on transmitter buffer empty condition, receive buffer full condition, error condition (receive, phase, baudrate, transmit error) ? three pin interface with flexible ssc pin configuration 3.13 watchdog timer the watchdog timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. the watchdog timer is always enabled after a reset of the chip, and can be disabled until the einit instruction has been executed (compatible mode), or it can be disabled and enabled at any time by executing instructions diswdt and enwdt (enhanced mode). thus, the chip?s start-up procedure is always monitored. the software has to be designed to restart the watchdog timer before it overflows. if, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and
xc164s derivatives functional description data sheet 39 v1.0, 2005-01 generates an internal hardware reset and pulls the rstout pin low in order to allow external hardware components to be reset. the watchdog timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/256. the high byte of the watchdog timer register can be set to a prespecified reload value (stored in wdtrel) in order to allow further variation of the monitored time interval. each time it is serviced by the application software, the high byte of the watchdog timer is reloaded and the low byte is cleared. thus, time intervals between 13 s and 419 ms can be monitored (@ 40 mhz). the default watchdog timer interval after reset is 3.28 ms (@ 40 mhz). 3.14 clock generation the clock generation unit uses a programmable on-chip pll with multiple prescalers to generate the clock signals for the xc164s with high flexibility. the master clock f mc is the reference clock signal and is output to the external system. the cpu clock f cpu and the system clock f sys are derived from the master clock ei ther directly (1:1) or via a 2:1 prescaler ( f sys = f cpu = f mc / 2). see also section 5.1 . the on-chip oscillator can drive an external crystal or accepts an external clock signal. the oscillator clock frequency can be multiplied by the on-chip pll (by a programmable factor) or can be divided by a programmable prescaler factor. if the bypass mode is used (direct drive or prescaler) the pll can deliver an independent clock to monitor the clock signal generated by the on-chip oscillator. this pll clock is independent from the xtal1 clock. when the expected oscillator clock transitions are missing the oscillator watchdog (owd) activates the pll unlock / owd interrupt node and supplies the cpu with an emergency clock, the pll clock signal. under these circumstances the pll will oscillate with its basic frequency. the oscillator watchdog can be disabled by switching the pll off. this reduces power consumption, but also no interrupt request will be generated in case of a missing oscillator clock. note: at the end of an external reset (ea = ?0?) the oscillator watchdog may be disabled via hardware by (externally) pulling the rd line low upon a reset, similar to the standard reset configuration. 3.15 parallel ports the xc164s provides up to 79 i/o lines which are organized into six input/output ports and one input port. all port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. the i/o ports are true bidirectional ports which are switched to high impedance state when configured as inputs. the output drivers of some i/o ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. during the internal reset, all port pins are configured as inputs (except for pin rstout ).
xc164s derivatives functional description data sheet 40 v1.0, 2005-01 the edge characteristics (shape) and driver characteristics (output current) of the port drivers can be selected via registers poconx. the input threshold of some ports is selectable (ttl or cmos like), where the special cmos like input threshold reduces noise sensitivity due to the input hysteresis. the input threshold may be selected individually for each byte of the respective ports. all port lines have programmable alternate input or output functions associated with them. all port lines that are not used for these alternate functions may be used as general purpose io lines.
xc164s derivatives functional description data sheet 41 v1.0, 2005-01 table 7 summary of the xc164s?s parallel ports port control alternate functions port0 pad drivers address/data lines or data lines 1) port1 pad drivers address lines 2) capture inputs or compare outputs, serial interface lines, fast external interrupt inputs port 3 pad drivers, open drain, input threshold timer control signals, serial interface lines, optional bus control signal bhe /wrh , system clock output clkout (or fout), debug interface lines port 4 pad drivers, open drain, input threshold segment address lines 3) optional chip select signals port 5 --- analog input channels to the a/d converter, timer control signals port 9 pad drivers, open drain, input threshold capture inputs or compare outputs port 20 pad drivers, open drain bus control signals rd , wr /wrl , ale, external access enable pin ea , reset indication output rstout 1) for multiplexed bus cycles. 2) for demultiplexed bus cycles. 3) for more than 64 kbytes of external resources.
xc164s derivatives functional description data sheet 42 v1.0, 2005-01 3.16 power management the xc164s provides several means to control the power it consumes either at a given time or averaged over a certain timespan. three mechanisms can be used (partly in parallel): ? power saving modes switch the xc164s into a special operating mode (control via instructions). idle mode stops the cpu while the peripherals can continue to operate. sleep mode and power down mode stop all clock signals and all operation (rtc may optionally continue running). sleep mode can be terminated by external interrupt signals. ? clock generation management controls the distribution and the frequency of internal and external clock signals. while the clock signals for currently inactive parts of logic are disabled automatically, the user can reduce the xc164s?s cpu clock frequency which drastically reduces the consumed power. external circuitry can be controlled via the programmable frequency output fout. ? peripheral management permits temporary disabling of peripheral modules (control via register syscon3). each peripheral can separately be disabled/enabled. the on-chip rtc supports intermittend operation of the xc164s by generating cyclic wake-up signals. this offers full performance to quickly react on action requests while the intermittend sleep phases greatly reduce the average power consumption of the system.
xc164s derivatives functional description data sheet 43 v1.0, 2005-01 3.17 instruction set summary table 8 lists the instructions of the xc164s in a condensed way. the various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the ?instruction set manual? . this document also provides a detailled description of each instruction. table 8 instruction set summary mnemonic description bytes add(b) add word (byte) operands 2 / 4 addc(b) add word (byte) operands with carry 2 / 4 sub(b) subtract word (byte) operands 2 / 4 subc(b) subtract word (byte) operands with carry 2 / 4 mul(u) (un)signed multiply direct gpr by direct gpr (16-16-bit) 2 div(u) (un)signed divide register mdl by direct gpr (16-/16-bit) 2 divl(u) (un)signed long divide reg. md by direct gpr (32-/16-bit) 2 cpl(b) complement direct word (byte) gpr 2 neg(b) negate direct word (byte) gpr 2 and(b) bitwise and, (word/byte operands) 2 / 4 (x)or(b) bitwise (exclusive)or, (word/byte operands) 2 / 4 bclr / bset clear/set direct bit 2 bmov(n) move (negated) direct bit to direct bit 4 band / bor / bxor and/or/xor direct bit with direct bit 4 bcmp compare direct bit to direct bit 4 bfldh / bfldl bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data 4 cmp(b) compare word (byte) operands 2 / 4 cmpd1/2 compare word data to gpr and decrement gpr by 1/2 2 / 4 cmpi1/2 compare word data to gpr and increment gpr by 1/2 2 / 4 prior determine number of shift cycles to normalize direct word gpr and store result in direct word gpr 2 shl / shr shift left/right direct word gpr 2 rol / ror rotate left/right direct word gpr 2 ashr arithmetic (sign bit) shift right direct word gpr 2 mov(b) move word (byte) data 2 / 4 movbs/z move byte operand to word op. with sign/zero extension 2 / 4
xc164s derivatives functional description data sheet 44 v1.0, 2005-01 jmpa/i/r jump absolute/indirect/relative if condition is met 4 jmps jump absolute to a code segment 4 jb(c) jump relative if direct bit is set (and clear bit) 4 jnb(s) jump relative if direct bit is not set (and set bit) 4 calla/i/r call absolute/indirect/relative subroutine if condition is met 4 calls call absolute subroutine in any code segment 4 pcall push direct word register onto system stack and call absolute subroutine 4 trap call interrupt service routine via immediate trap number 2 push / pop push/pop direct word register onto/from system stack 2 scxt push direct word register onto system stack and update register with word operand 4 ret(p) return from intra-segment subroutine (and pop direct word register from system stack) 2 rets return from inter-segment subroutine 2 reti return from interrupt service subroutine 2 sbrk software break 2 srst software reset 4 idle enter idle mode 4 pwrdn enter power down mode (supposes nmi -pin being low) 4 srvwdt service watchdog timer 4 diswdt/enwdt disable/enable watchdog timer 4 einit signify end-of-initialization on rstout-pin 4 atomic begin atomic sequence 2 extr begin extended register sequence 2 extp(r) begin extended page (and register) sequence 2 / 4 exts(r) begin extended segment (and register) sequence 2 / 4 nop null operation 2 comul / comac multiply (and accumulate) 4 coadd / cosub add / subtract 4 co(a)shr/coshl (arithmetic) shift right / shift left 4 coload/store load accumulator / store mac register 4 cocmp/max/min compare (maximum/minimum) 4 coabs / cornd absolute value / round accumulator 4 comov/neg/nop data move / negate accumulator / null operation 4 table 8 instruction set summary (cont?d) mnemonic description bytes
xc164s derivatives electrical parameters data sheet 45 v1.0, 2005-01 4 electrical parameters 4.1 absolute maximum ratings note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during absolute maximum rating overload conditions ( v in > v ddp or v in < v ss ) the voltage on v ddp pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. 4.2 package properties table 9 absolute maximum rating parameters parameter symbol limit values unit notes min. max. storage temperature t st -65 150 c? junction temperature t j -40 150 c under bias voltage on v ddi pins with respect to ground ( v ss ) v ddi -0.5 3.25 v ? voltage on v ddp pins with respect to ground ( v ss ) v ddp -0.5 6.2 v ? voltage on any pin with respect to ground ( v ss ) v in -0.5 v ddp + 0.5 v? input current on any pin during overload condition ?-1010ma? absolute sum of all input currents during overload condition ? ? |100| ma ? table 10 package parameters (p-tqfp-100-16) parameter symbol limit values unit notes min. max. power dissipation p diss ?0.8w? thermal resistance r tha ? 29 k/w chip-ambient
xc164s derivatives electrical parameters data sheet 46 v1.0, 2005-01 4.3 operating conditions the following operating conditions must not be exceeded to ensure correct operation of the xc164s. all parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. table 11 operating condition parameters parameter symbol limit values unit notes min. max. digital supply voltage for the core v ddi 2.35 2.7 v active mode, f cpu = f cpumax 1) 1) f cpumax = 40 mhz for devices marked 40f, f cpumax = 20 mhz for devices marked 20f. digital supply voltage for io pads v ddp 4.4 5.5 v active mode 2) 3) 2) external circuitry must guarantee low level at the rstin pin at least until both power supply voltages have reached the operating level. 3) the specified voltage range is allowed for operation. the range limits may be reached under extreme operating conditions. however, specified parameters, such as leakage currents, refer to the standard operating voltage range of v ddp = 4.75 v to 5.25 v. supply voltage difference ? v dd -0.5 ? v v ddp - v ddi 4) 4) this limitation must be fulfilled under all operating conditions including power-ramp-up, power-ramp-down, and power-save modes. digital ground voltage v ss 0 v reference voltage overload current i ov -5 5 ma per io pin 5)6) -2 5 ma per analog input pin 5)6) overload current coupling factor for analog inputs 7) k ova ?1.0 10 -4 ? i ov > 0 ?1.5 10 -3 ? i ov < 0 overload current coupling factor for digital i/o pins 7) k ovd ?5.0 10 -3 ? i ov > 0 ?1.0 10 -2 ? i ov < 0 absolute sum of overload currents | i ov |? 50 ma 6) external load capacitance c l ? 50 pf pin drivers in default mode 8) ambient temperature t a 070 c sab-xc164s ? -40 85 c saf-xc164s ? -40 125 c sak-xc164s ?
xc164s derivatives electrical parameters data sheet 47 v1.0, 2005-01 4.4 parameter interpretation the parameters listed in the following partly represent the characteristics of the xc164s and partly its demands on the system. to aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ?symbol?: cc ( c ontroller c haracteristics): the logic of the xc164s will provide signals with the respective characteristics. sr ( s ystem r equirement): the external system must provide signals with the respective characteristics to the xc164s. 5) overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range: v ov > v ddp + 0.5 v ( i ov >0) or v ov < v ss - 0.5 v ( i ov < 0). the absolute sum of input overload currents on all pins may not exceed 50 ma . the supply voltages must remain within the specified limits. proper operation is not guaranteed if overload conditions occur on functional pins such as xtal1, rd , wr , etc. 6) not subject to production test - verified by design/characterization. 7) an overload current ( i ov ) through a pin injects a certain error current ( i inj ) into the adjacent pins. this error current adds to the respective pin?s leakage current ( i oz ). the amount of error current depends on the overload current and is defined by the overload coupling factor k ov . the polarity of the injected error current is inverse compared to the polarity of the overload current that produces it. the total current through a pin is | i tot | = | i oz | + (| i ov | k ov ). the additional error current may distort the input voltage on analog inputs. 8) the timing is valid for pin drivers operating in default current mode (selected after reset). reducing the output current may lead to increased delays or reduced driving capability ( c l ).
xc164s derivatives electrical parameters data sheet 48 v1.0, 2005-01 4.5 dc parameters dc characteristics (operating conditions apply) 1) parameter symbol limit values unit test condition min. max. input low voltage ttl (all except xtal1) v il sr -0.5 0.2 v ddp - 0.1 v? input low voltage xtal1 v ilc sr -0.5 0.3 v ddi v? input low voltage (special threshold) v ils sr -0.5 0.45 v ddp v 2) input high voltage ttl (all except xtal1) v ih sr 0.2 v ddp + 0.9 v ddp + 0.5 v? input high voltage xtal1 v ihc sr 0.7 v ddi v ddi + 0.5 v? input high voltage (special threshold) v ihs sr 0.8 v ddp - 0.2 v ddp + 0.5 v 2) input hysteresis (special threshold) hys 0.04 v ddp ?v v ddp in [v], series resis- tance = 0 ? 2) output low voltage v ol cc ? 1.0 v i ol i olmax 3) ?0.45v i ol i olnom 3) 4) output high voltage 5) v oh cc v ddp - 1.0 ?v i oh i ohmax 3) v ddp - 0.45 ?v i oh i ohnom 3) 4) input leakage current (port 5) 6) i oz1 cc ? 300 na 0 v < v in < v ddp, t a 125 c 200 na 0 v < v in < v ddp, t a 85 c 12) input leakage current (all other) 6) i oz2 cc ? 500 na 0.45 v < v in < v ddp configuration pull-up current 7) i cpuh 8) ?-10 a v in = v ihmin i cpul 9) -100 ? a v in = v ilmax
xc164s derivatives electrical parameters data sheet 49 v1.0, 2005-01 configuration pull-down current 10) i cpdl 8) ?10 a v in = v ilmax i cpdh 9) 120 ? a v in = v ihmin level inactive hold current 11) i lhi 8) ?-10 a v out = 0.5 v ddp level active hold current 11) i lha 9) -100 ? a v out = 0.45 v xtal1 input current i il cc ? 20 a0 v < v in < v ddi pin capacitance 12) (digital inputs/outputs) c io cc ? 10 pf 1) keeping signal levels within the limits specified in this table, ensures operation without overload conditions. for signal levels outside these specifications, also refer to the specification of the overload current i ov . 2) this parameter is tested for p2, p3, p4, p9. 3) the maximum deliverable output current of a port driver depends on the selected output driver mode, see table 12 , current limits for port output drivers . the limit for pin groups must be respected. 4) as a rule, with decreasing output current the output levels approach the respective supply level ( v ol v ss , v oh v ddp ). however, only the levels for nominal output currents are guaranteed. 5) this specification is not valid for outputs which are switched to open drain mode. in this case the respective output will float and the voltage results from the external circuitry. 6) an additional error current ( i inj ) will flow if an overload current flows through an adjacent pin. please refer to the definition of the overload coupling factor k ov . 7) this specification is valid during reset for configuration on rd , wr , ea , port0. 8) the maximum current may be drawn while the respective signal line remains inactive. 9) the minimum current must be drawn to drive the respective signal line active. 10) this specification is valid during reset for configuration on ale. 11) this specification is valid during reset for pins p4.3-0, which can act as cs outputs. 12) not subject to production test - verified by design/characterization. dc characteristics (cont?d) (operating conditions apply) 1) parameter symbol limit values unit test condition min. max.
xc164s derivatives electrical parameters data sheet 50 v1.0, 2005-01 table 12 current limits for port output drivers port output driver mode maximum output current ( i olmax , - i ohmax ) 1) nominal output current ( i olnom , - i ohnom ) strong driver 10 ma 2.5 ma medium driver 4.0 ma 1.0 ma weak driver 0.5 ma 0.1 ma 1) an output current above | i oxnom | may be drawn from up to three pins at the same time. for any group of 16 neighboring port output pins the total output current in each direction ( i ol and - i oh ) must remain below 50 ma. power consumption xc164s (operating conditions apply) parameter symbol limit values unit test condition min. max. power supply current (active) with all peripherals active i ddi ?15 + 2.6 f cpu ma 1) f cpu in [mhz] 2) 1) during flash programming or erase operations the supply current is increased by max. 5 ma. 2) the supply current is a function of the operating frequency. this dependency is illustrated in figure 10 . these parameters are tested at v ddimax and maximum cpu clock frequency with all outputs disconnected and all inputs at v il or v ih . pad supply current i ddp ?5 ma 3) 3) the pad supply voltage pins ( v ddp ) mainly provides the current consumed by the pin output drivers. a small amount of current is consumed even though no outputs are driven, because the drivers? input stages are switched and also the flash module draws some power from the v ddp supply. idle mode supply current with all peripherals active i idx ?15 + 1.2 f cpu ma f cpu in [mhz] 2) sleep and power-down mode supply current caused by leakage 4) 4) the total supply current in sleep and power-down mode is the sum of the temperature dependent leakage current and the frequency dependent current for rtc and main oscillator (if active). i pdl 5) ?128,000 e - ma v ddi = v ddimax 6) t j in [c] = 4670/(273+ t j ) sleep and power-down mode supply current caused by leakage and the rtc running, clocked by the main oscillator 4) i pdm 7) ?0.6 + 0.02 f osc + i pdl ma v ddi = v ddimax f osc in [mhz]
xc164s derivatives electrical parameters data sheet 51 v1.0, 2005-01 5) this parameter is determined mainly by the transistor leakage currents. this current heavily depends on the junction temperature (see figure 12 ). the junction temperature t j is the same as the ambient temperature t a if no current flows through the port output drivers. otherwise, the resulting temperature difference must be taken into account. 6) all inputs (including pins configured as inputs) at 0 v to 0.1 v or at v ddp - 0.1 v to v ddp , all outputs (including pins configured as outputs) disconnected. this parameter is tested at 25 c and is valid for t j 25 c. 7) this parameter is determined mainly by the current consumed by the oscillator switched to low gain mode (see figure 11 ). this current, however, is influenced by the external oscillator circuitry (crystal, capacitors). the given values refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry.
xc164s derivatives electrical parameters data sheet 52 v1.0, 2005-01 figure 10 supply/idle current as a function of operating frequency i [ma] f cpu [mhz] 10 20 30 40 i ddimax i ddityp i idxmax i idxtyp 20 40 60 80 100 120 140
xc164s derivatives electrical parameters data sheet 53 v1.0, 2005-01 figure 11 sleep and power down supply current due to rtc and oscillator running, as a function of oscillator frequency figure 12 sleep and power down leakage supply current as a function of temperature i [ma] f osc [mhz] 4 8 12 16 i pdmmax i pdmtyp 1.0 2.0 3.0 i pdamax 0.1 32 khz [ma] t j [c] 0 50 100 150 i pdo 0.5 1.0 1.5 -50
xc164s derivatives electrical parameters data sheet 54 v1.0, 2005-01 4.6 a/d converter characteristics table 13 a/d converter characteristics (operating conditions apply) parameter symbol limit values unit test condition min. max. analog reference supply v aref sr 4.5 v ddp + 0.1 v 1) 1) tue is tested at v aref = v ddp +0.1v, v agnd = 0 v. it is verified by design for all other voltages within the defined voltage range. if the analog reference supply voltage drops below 4.5 v (i.e. v aref 4.0 v) or exceeds the power supply voltage by up to 0.2 v (i.e. v aref = v ddp + 0.2 v) the maximum tue is increased to 3 lsb. this range is not subject to production test. the specified tue is guaranteed only, if the absolute sum of input overload currents on port 5 pins (see i ov specification) does not exceed 10 ma, and if v aref and v agnd remain stable during the respective period of time. during the reset calibration sequence the maximum tue may be 4lsb. analog reference ground v agnd sr v ss - 0.1 v ss + 0.1 v analog input voltage range v ain sr v agnd v aref v 2) basic clock frequency f bc 0.5 20 mhz 3) conversion time for 10-bit result 4) t c10p cc 52 t bc + t s + 6 t sys ? post-calibr. on t c10 cc 40 t bc + t s + 6 t sys ? post-calibr. off conversion time for 8-bit result 4) t c8p cc 44 t bc + t s + 6 t sys ? post-calibr. on t c8 cc 32 t bc + t s + 6 t sys ? post-calibr. off calibration time after reset t cal cc 484 11,696 t bc 5) total unadjusted error tue cc ? 2lsb 1) total capacitance of an analog input c aint cc ?15pf 6) switched capacitance of an analog input c ains cc ?10pf 6) resistance of the analog input path r ain cc ?2k ? 6) total capacitance of the reference input c areft cc ?20pf 6) switched capacitance of the reference input c arefs cc ?15pf 6) resistance of the reference input path r aref cc ?1k ? 6)
xc164s derivatives electrical parameters data sheet 55 v1.0, 2005-01 figure 13 equivalent circuitry for analog inputs 2) v ain may exceed v agnd or v aref up to the absolute maximum ratings. however, the conversion result in these cases will be x000 h or x3ff h , respectively. 3) the limit values for f bc must not be exceeded when selecting the peripheral frequency and the adctc setting. 4) this parameter includes the sample time t s , the time for determining the digital result and the time to load the result register with the conversion result ( t sys = 1 / f sys ). values for the basic clock t bc depend on programming and can be taken from table 14 . when the post-calibration is switched off, the conversion time is reduced by 12 x t bc 5) the actual duration of the reset calibration depends on the noise on the reference signal. conversions executed during the reset calibration increase the calibration time. the tue for those conversions may be increased. 6) not subject to production test - verified by design/characterization. the given parameter values cover the complete operating range. under relaxed operating conditions (temperature, supply voltage) reduced values can be used for calculations. at room temperature and nominal supply voltage the following typical values can be used: c ainttyp = 12 pf, c ainstyp = 7 pf, r aintyp = 1.5 k ? , c arefttyp = 15 pf, c arefstyp = 13 pf, r areftyp = 0.7 k ? . mcs04879_p.vsd r source = v ain c ext r ain, on c aint - c ains c ains a/d converter
xc164s derivatives electrical parameters data sheet 56 v1.0, 2005-01 sample time and conversion time of the xc164s?s a/d converter are programmable. in compatibility mode, the above timing can be calculated using table 14 . the limit values for f bc must not be exceeded when selecting adctc. converter timing example: assumptions: f sys = 40 mhz (i.e. t sys = 25 ns), adctc = ?01?, adstc = ?00?. basic clock f bc = f sys / 2 = 20 mhz, i.e. t bc = 50 ns. sample time t s = t bc 8 = 400 ns. conversion 10-bit: with post-calibr. t c10p = 52 t bc + t s + 6 t sys = (2600 + 400 + 150) ns = 3.15 s. post-calibr. off t c10 = 40 t bc + t s + 6 t sys = (2000 + 400 + 150) ns = 2.55 s. conversion 8-bit: with post-calibr. t c8p = 44 t bc + t s + 6 t sys = (2200 + 400 + 150) ns = 2.75 s. post-calibr. off t c8 = 32 t bc + t s + 6 t sys = (1600 + 400 + 150) ns = 2.15 s. table 14 a/d converter computation table 1) 1) these selections are available in compatibility mode. an improved mechanism to control the adc input clock can be selected. adcon.15|14 (adctc) a/d converter basic clock f bc adcon.13|12 (adstc) sample time t s 00 f sys / 4 00 t bc 8 01 f sys / 2 01 t bc 16 10 f sys / 16 10 t bc 32 11 f sys / 8 11 t bc 64
xc164s derivatives timing parameters data sheet 57 v1.0, 2005-01 5 timing parameters 5.1 definition of internal timing the internal operation of the xc164s is controlled by the internal master clock f mc . the master clock signal f mc can be generated from the oscillator clock signal f osc via different mechanisms. the duration of master clock periods (tcms) and their variation (and also the derived external timing) depend on the used mechanism to generate f mc . this influence must be regarded when calculating the timings for the xc164s. figure 14 generation mechanisms for the master clock note: the example for pll operation shown in figure 14 refers to a pll factor of 1:4, the example for prescaler operation refers to a divider factor of 2:1. the used mechanism to generate the master clock is selected by register pllcon. cpu and ebc are clocked with the cpu clock signal f cpu . the cpu clock can have the same frequency as the master clock ( f cpu = f mc ) or can be the master clock divided by two: f cpu = f mc / 2. this factor is selected by bit cpsys in register syscon1. the specification of the external timing (ac characteristics) depends on the period of the cpu clock, called ?tcp?. the other peripherals are supplied with the system clock signal f sys which has the same frequency as the cpu clock signal f cpu . tcm tcm f mc f osc f mc f osc phase locked loop operation (1:n) direct clock drive (1:1) tcm f mc f osc prescaler operation (n:1)
xc164s derivatives timing parameters data sheet 58 v1.0, 2005-01 bypass operation when bypass operation is configured (pllctrl = 0x b ) the master clock is derived from the internal oscillator (input clock signal xtal1) through the input- and output- prescalers: f mc = f osc / ((pllidiv+1) (pllodiv+1)). if both divider factors are selected as ?1? (p llidiv = pllodiv = ?0?) the frequency of f mc directly follows the frequency of f osc so the high and low time of f mc is defined by the duty cycle of the input clock f osc . the lowest master clock frequency is achieved by selecting the maximum values for both divider factors: f mc = f osc / ((3+1) (14+1)) = f osc / 60. phase locked loop (pll) when pll operation is configured (pllctrl = 11 b ) the on-chip phase locked loop is enabled and provides the master clock. t he pll multiplies the input frequency by the factor f ( f mc = f osc f ) which results from the input divider, the multiplication factor, and the output divider ( f = pllmul+1 / (pllidiv+1 pllodiv+1)). the pll circuit synchronizes the master clock to the input clock. this synchronization is done smoothly, i.e. the master clock frequency does not change abruptly. due to this adaptation to the input clock the frequency of f mc is constantly adjusted so it is locked to f osc . the slight variation causes a jitter of f mc which also affects the duration of individual tcms. the timing listed in the ac characteristics refers to tcps. because f cpu is derived from f mc , the timing must be calculated using the minimum tcp possible under the respective circumstances. the actual minimum value for tcp depends on the jitter of the pll. as the pll is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one tcp is lower than for one single tcp (see formula and figure 15 ). this is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. for all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the pll jitter is negligible. the value of the accumulated pll jitter depends on the number of consecutive vco output cycles within the respective timeframe. the vco output clock is divided by the output prescaler (k = pllodiv+1) to generate the master clock signal f mc . therefore, the number of vco cycles can be represented as k n , where n is the number of consecutive f mc cycles (tcm).
xc164s derivatives timing parameters data sheet 59 v1.0, 2005-01 for a period of n tcm the accumulated pll jitter is defined by the deviation d n : d n [ns] = (1.5 + 6.32 n / f mc ); f mc in [mhz], n = number of consecutive tcms. so, for a period of 3 tcms @ 20 mhz and k = 12: d 3 = (1.5 + 6.32 3 / 20) = 2.448 ns. this formula is applicable for k n < 95. for longer periods the k n =95 value can be used. this steady value can be approximated by: d n max [ns] = (1.5 + 600 / (k f mc )). figure 15 approximated accumulated pll jitter note: the bold lines indicate the minimum accumulated jitter which can be achieved by selecting the maximum possible output prescaler factor k. different frequency bands can be selected for the vco, so the operation of the pll can be adjusted to a wide range of input and output frequencies: table 15 vco bands for pll operation 1) 1) not subject to production test - verified by design/characterization. pllcon.pllvb vco frequency range base frequency range 00 100 150 mhz 20 80 mhz 01 150 200 mhz 40 130 mhz 10 200 250 mhz 60 180 mhz 11 reserved mcb04413_xc.vsd acc. jitter d n 8 6 ns 4 2 1 0 510 20 25 n 1 0 m h z k=5 2 0 m h z 4 0 m h z 7 5 3 15 k=6 k=12 k=15 k=8 k=10 1
xc164s derivatives timing parameters data sheet 60 v1.0, 2005-01 5.2 external clock drive xtal1 figure 16 external clock drive xtal1 note: if the on-chip oscillator is used together with a crystal or a ceramic resonator, the oscillator frequency is limited to a range of 4 mhz to 16 mhz. it is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimum parameters for the oscillator operation. please refer to the limits specified by the crystal supplier. when driven by an external clock signal it will accept the specified frequency range. operation at lower input frequencies is possible but is verified by design only (not subject to production test). table 16 external clock drive characteristics (operating conditions apply) parameter symbol limit values unit min. max. oscillator period t osc sr 20 250 1) 1) the maximum limit is only relevant for pll operation to ensure the minimum input frequency for the pll. ns high time 2) 2) the clock input signal must reach the defined levels v ilc and v ihc . t 1 sr 6 ? ns low time 2) t 2 sr 6 ? ns rise time 2) t 3 sr ? 8 ns fall time 2) t 4 sr ? 8 ns mct05138 3 t 4 t v ihc v ilc v ddi 0.5 1 t 2 t osc t
xc164s derivatives timing parameters data sheet 61 v1.0, 2005-01 5.3 testing waveforms figure 17 input output waveforms figure 18 float waveforms 0.45 v 0.8 v 2.0 v input signal (driven by tester) output signal (measured) mca00763 - 0.1 v + 0.1 v + 0.1 v - 0.1 v reference for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, but begins to float when a 100 mv change from the loaded oh v timing points load v v load oh v v ol / v ol level occurs ( i oh ol i / = 20 ma).
xc164s derivatives timing parameters data sheet 62 v1.0, 2005-01 5.4 ac characteristics figure 19 clkout signal timing table 17 clkout reference signal parameter symbol limits unit min. max. clkout cycle time tc 5 cc 50/25 1) 1) the clkout cycle time is influenced by the pll jitter (given values apply to f cpu =20/40 mhz). for longer periods the relative deviation decreases (see pll deviation formula). ns clkout high time tc 6 cc 8 ? ns clkout low time tc 7 cc 6 ? ns clkout rise time tc 8 cc ? 4 ns clkout fall time tc 9 cc ? 4 ns mct04415 clkout tc 5 tc 6 7 tc 8 tc 9 tc
xc164s derivatives timing parameters data sheet 63 v1.0, 2005-01 variable memory cycles external bus cycles of the xc164s are executed in five subsequent cycle phases (ab, c, d, e, f). the duration of each cycle phase is programmable (via the tconcsx registers) to adapt the external bus cycles to the respective external module (memory, peripheral, etc.). this table provides a summary of the phases and the respective choices for their duration. the specification of the external timing depends on the period of the cpu clock, which is called ?tcp? and is used in table 18 note: the bandwidth of a parameter (minimum and maximum value) covers the whole operating range (temperature, voltage) as well as process variations. within a given device, however, this bandwidth is smaller than the specified range. this is also due to interdependencies between certain parameters. some of these interdependencies are described in additional notes (see standard timing). table 18 programmable bus cycle phases (see timing diagrams) bus cycle phase parameter valid values unit address setup phase, the standard duration of this phase (1 2 tcp) can be extended by 0 3 tcp if the address window is changed tp ab 1 2 (5) tcp command delay phase tp c 0 3 tcp write data setup / mux tristate phase tp d 0 1 tcp access phase tp e 1 32 tcp address / write data hold phase tp f 0 3 tcp
xc164s derivatives timing parameters data sheet 64 v1.0, 2005-01 note: the shaded parameters have been verified by characterization. they are not subject to production test. table 19 external bus cycle timing (operating conditions apply) parameter symbol limits unit min. max. output valid delay for: rd , wr (l /h ) tc 10 cc 115ns output valid delay for: bhe , ale tc 11 cc -1 8 ns output valid delay for: a23 a16, a15 a0 (on port1) tc 12 cc 318ns output valid delay for: a15 a0 (on port0) tc 13 cc 318ns output valid delay for: cs tc 14 cc 316ns output valid delay for: d15 d0 (write data, mux-mode) tc 15 cc 319ns output valid delay for: d15 d0 (write data, demux-mode) tc 16 cc 216ns output hold time for: rd , wr (l /h ) tc 20 cc -3 4ns output hold time for: bhe , ale tc 21 cc 0 11 ns output hold time for: a23 a16, a15 a0 (on port0) tc 23 cc 1 13 ns output hold time for: cs tc 24 cc -2 4ns output hold time for: d15 d0 (write data) tc 25 cc 1 13 ns input setup time for: d15 d0 (read data) tc 30 sr 29 ? ns input hold time d15 d0 (read data) 1) tc 31 sr -5 ? ns 1) read data are latched with the same (internal) clock edge that triggers the address change and the rising edge of rd . therefore address changes before the end of rd have no impact on (demultiplexed) read cycles. read data can be removed after the rising edge of rd
xc164s derivatives timing parameters data sheet 65 v1.0, 2005-01 figure 20 multiplexed bus cycle a23-a16, bhe , csx clkout ale tc 21 rd wr (l /h ) tc 11 tc 11 | tc 14 ad15-ad0 (read) data out low address tc 10 tc 20 tc 13 tc 23 ad15-ad0 (write) tc 13 tc 15 low address data in high address tp ab tp c tp d tp e tp f tc 31 tc 30 tc 25
xc164s derivatives timing parameters data sheet 66 v1.0, 2005-01 figure 21 demultiplexed bus cycle a23-a0, bhe , csx clkout ale tc 21 rd wr (l /h ) tc 11 tc 11 | tc 14 d15-d0 (read) data out tc 10 tc 20 d15-d0 (write) tc 16 data in address tp ab tp c tp d tp e tp f tc 31 tc 30 tc 25
xc164s derivatives packaging data sheet 67 v1.0, 2005-01 6 packaging figure 22 package outlines p-tqfp-100-16 (plastic thin quad flat package) dimensions in mm. you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products
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